The present invention relates to semiconductor chip fabrication, and more specifically, to semiconductor chip timing analysis and optimization.
Semiconductor chip fabrication typically includes benchmark tests which require the semiconductor chip to pass timing and/or frequency targets before proceeding to the manufacturing stage. To manage complexity and aid parallel development, various semiconductor chips (e.g., microprocessors) are designed according to a hierarchical scheme which includes, for example, a macro level, a unit level and a core level. Each macro/unit/core has a contract or timing specification that is expected to be satisfied.
The macro level comprises of a plurality of macro circuits including a plurality of logic gates connected to one another via at least one electrically conductive path. The unit level comprises at least one unit components including at least one macro circuit. The core level comprises one or more core components including at least one unit component. An input or output of a respective gate or respective wire at the macro level is typically referred to as a node, while a connection between different nodes (e.g., a first node and a second node) is typically referred to as an arc. That is, an arc indicates, for example, how a first node is connected to a second node.
When performing timing analysis of the macro level, conventional methods have relied on circuit simulation techniques which achieve high accuracy analysis results. These conventional circuit simulation techniques, however, tend to be run time prohibitive and thus may prove to be inefficient especially if multiple instances exist where portions of macro level, unit level and/or core level do not require timing analysis.